Metal oxide semi-conductor circuits are extensively utilized as memories in data processing systems. In dynamic MOS memories, data are stored as quantities of charge in parasitic capacitors between a gate and drain electrode of an MOS field effect transistor (FET). Because the parasitic capacitor has substantial leakage, it is necessary to combine the capacitor with a device for recharging the capacitor periodically to preserve the stored data value, such recharging is generally referred to as a refresh operation. The refresh operation is performed typically under the control of a data processing system of which the memory is a part.
The memory is controlled by the data processing system so that the memory is operating either in a refresh cycle or in a useful cycle. During a refresh cycle, charge is restored to the parasitic capacitors. During a useful cycle, the data processing system of which the memory is a part, has access to the memory so that stored data are exchanged between the memory and the data processor, whereby elementary data processing operations can be performed by the data processing system during the useful cycles. In contrast, during the regeneration or refresh cycles, the data processing system does not have access to data stored in the memory. It is thus important to minimize the total time that the memory is being refreshed. Generally, calls for useful and refresh cycles of the memory by the data processing system are assynchronous, and the data processing system must constantly resynchronize the useful and refresh cycles in order to select them.
In one prior art system, a selective decision is made at the beginning of each useful or refresh cycle. In the prior art system, the period required for a selective decision at the beginning of each cycle is approximately several hundred nanoseconds. The selective decision period is followed by approximately twenty (20) nanoseconds, during which addressing circuit switching and preparation operations are performed. A random access, MOS dynamic memory is thus unavailable to the remainder of a data processing system of which it is a part for an interval of approximately one hundred and twenty (120) nanoseconds during each cycle, before a useful or refresh cycle is actually initiated. The unavailability of the memory to the data processing system is increased during elementary operations wherein data are read from a memory block or cell, since the time required to acquire the data is systematically prolonged by the selection time; the time required to acquire the information is frequently referred to as the data access time.
It is, accordingly, an object of the present invention to provide a new and improved method and apparatus for reducing the total cycle time in a refresh, MOS, random access memory.
A further object of the invention is to provide a new and improved apparatus for and method of refreshing an MOS, random access, dynamic memory wherein data selection intervals are not systematically added to cycle time of the memory.
An additional object of the present invention is to provide a new and improved apparatus for and method of operating a random access, dynamic MOS memory wherein data access time is reduced by the period required for selection of a refresh or useful cycle.